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參數資料
型號： W90221F
廠商： WINBOND ELECTRONICS CORP
英文描述： PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器)
中文描述： PA - RISC的嵌入式微控制器（惠普的PA - RISC結構的32位嵌入式微控制器）
文件頁數： 29/174頁
文件大?。?/td> 2102K
代理商： W90221F
=
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
29
Versi on 0. 4, March/2000
- IRDY# (inout) :
IRDY# is an output when W90221 acts as an initiator on the PCI bus and an input when W90221
acts as a PCI target. The assertion of TRDY# indicates the current PCI bus initiator can complete
the current data phase of the transaction.
- TRDY# (inout) :
TRDY# is an input when W90221 acts as an initiator on the PCI bus and an output when W90221
acts as a PCI target. The assertion of IRDY# indicates the current PCI target can complete the
current data phase of the transaction.
- STOP# (inout) :
STOP# is an input when W90221 acts as an initiator on the PCI bus and an output when W90221
acts as a PCI target. STOP# is used for disconnect, retry, and abort sequences on the PCI bus.
- DEVSEL# (inout) :
Device select, when asserted, indicates that a PCI target device has decoded its address as the
target of the current access. The W90221 asserts DEVSEL# based on the DRAM address
range
being accessed by a PCI initiator. As an input it indicates whether any device on the bus
has been
selected.
- PERR# (inout) :
PERR# indicates the current transaction has data parity error occurs. it is an input when W90221
acts as an PCI initiator and the current transaction is write access or W90221 acts as an PCI target
and the current transaction is read access. it is an output when W90221 acts as PCI initiator
and
the current transaction is read access or W90221 acts as an PCI target and the current
transaction
is write access. When PERR# asserted and Master 0 Latency Register bit 17=1, it will
genwrate
NMI (non-maskable interrupt).
- PPAR# (inout) :
PPAR# is driven by the W90221 when it acts as a PCI initiator during address and data
phases for
a write cycle, and during the address phase for a read cycle. PPAR is driven by the W90221
when
it acts as a PCI target during each data phase of a PCI memory read cycle. Even parity is
generated across PDA[31:0] and COMBE#[3:0].
PCI bus command and byte enable signals are multiplexed on the same pins. During the address
phase of a transaction, COMBE#[3:0] define the bus command. During the data phase,
COMBE#[3:0] are used as byte enables. The byte enables deterrmine which byte lanes carry
meaningful data. The provided bus command encoding and types are listed below :
COMBE#[3:0] Command type
0010
0011 I/O write
0110 Memory read
0111 Memory write
1010
Configuration read
1011 Configuration write
I/O read
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