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參數(shù)資料
型號： W90221F
廠商： WINBOND ELECTRONICS CORP
英文描述： PA-RISC Embedded Micro-Controller(惠普PA-RISC結(jié)構(gòu)的32位嵌入式微控制器)
中文描述： PA - RISC的嵌入式微控制器（惠普的PA - RISC結(jié)構(gòu)的32位嵌入式微控制器）
文件頁數(shù)： 7/174頁
文件大小： 2102K
代理商： W90221F
=
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
7
Versi on 0. 4, March/2000
4. DETAIL PIN DESCRIPTIONS
The following abbreviations are used for pin types in the following sections : (I) indicates inputs; (O)
indicates
outputs; (I/O) indicates a bi-directional signal; (TS) indicates three-state; (OC) indicates open collector. (AO)
indicates analog output; (AI) indicates analog input;
PIN Name
DIR
PIN #
DESCRIPTION
System Reset and Clock :
PWRON
I
8
CPU Power-On reset input, high active
DPCLK
I
199
This clock source serves as internal PLL input as well as
VA's system clock. A precise
27MHz
clock source shall be
connected to this pin during normal operation.
GFXCLK
I
96
This clock source serves as pixel clock, 36MHz to 50MHz,
using in 800x600 non-interlace monitor. For TV subsystem,
this clock may pull high or low externally. Meanwhile,
GFXCLK may also serves as system OSC (for baud rate or
timer adjustment), if
MD[24]
is pull high externally.
General Purpose I/O pins :
GPIO[0:7]
I/O
138-145
If parallel port is enable (port 0x3e[4] = 1), these pins serve
as bi-directional ECP data bus "
ED[0:7]
" with ED[0] is the
most significant bit (inout).
If parallel port is not enable (port 0x3e[4:5] = 0x), these pins
provide general purpose I/O functionality (inout).
GPIO[8]
I/O
146
If parallel port is enable (port 0x3e[4:5] = 1x), this pin serve
as ECP "
nInit
" (output).
If parallel port is not enable (port 0x3e[4:5] = 0x), this pin
provides general purpose I/O functionality (inout)
GPIO[9]
I/O
148
If parallel port is enable (port 0x3e[4:5] = 1x), this pin serve
as ECP "
nSelectIn
" (output).
If parallel port is not enable (port 0x3e[4:5] = 0x), this pin
provides general purpose I/O functionality (inout)
GPIO[10]
I/O
149
If parallel port is enable (port 0x3e[4] = 1x), this pin serve as
ECP "
Select
" (input).
If parallel port is not enable (port 0x3e[4:5] = 00), this pin
provides general purpose I/O functionality (inout).
During "clock test" mode (port 0x3e[4] = 01), this pin outputs
internal
CPUCLK
(output).
GPIO[11]
I/O
150
If parallel port is enable (port 0x3e[4] = 1x), this pin serve as
ECP "
PError
" (input).
If parallel port is not enable (port 0x3e[4:5] = 00), this pin
provides general purpose I/O functionality (inout).
During "clock test" mode (port 0x3e[4] = 01), this pin outputs
internal
MCLK_ctl
(output).
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