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參數(shù)資料
| 型號(hào)： | W90221F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結(jié)構(gòu)的32位嵌入式微控制器) |
| 中文描述： | PA - RISC的嵌入式微控制器（惠普的PA - RISC結(jié)構(gòu)的32位嵌入式微控制器） |
| 文件頁(yè)數(shù)： | 38/174頁(yè) |
| 文件大小： | 2102K |
| 代理商： | W90221F |
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The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
38
Versi on 0. 4, March/2000
operation.
IIR bits
a
- Polled Mode operation : (refer to "LSR" register discriptions located on Section 5.2.5)
- No interrupts need be enabled at this mode, the CPU always polls the LSR to check COM port status
before
taking any actions.
- LSR[7] will be set as long as there is at least one byte in the RX-FIFO, and it is cleared if the RX-FIFO
is
empty.
- LSR[3:6] will specify error(s) status which is handled the same way as in the interrupt mode operation,
the
IIR[4:7] is not affected since no interrupt is enabled.
- LSR[2] will indicate when the TX-FIFO is empty.
- LSR[1] will indicate that both TX-FIFO and shift register are empty.
- LSR[0] will indicate whether there are any errors in the RX-FIFO.
- Set IER[6] to logic 1 to enable "transmitter empty interrupt" (Irpt_THRE) before transmitter
- Once the transmitter FIFO (TX-FIFO) is empty, the Irpt_THRE is triggered and the corresponding
are set to inform the CPU to fill the TX-FIFO (maximum 16 bytes of characters).
- The Irpt_THRE is reset after the CPU reads the IIR (IIR[4:7] must be 4'b0010 at that time) or writes
character into TX-FIFO.
- Irpt_RDA and Irpt_TOUT has the same interrupt priority (2nd priority) while Irpt_THRE has a lower
priority (3rd priority).
5.11 SYNCHRONOUS SERIAL INTERFACE (SSI)
Overview :
The SSI module within W90221 contains holding registers, shift registers, and other logic to support a
variety of serial data communications protocols and provide a direct connection to external audio/telephony
codec devices.
Two 48 halfwords fifos, the transmitter fifo and receiver fifo, have been implented to accelerate both
transmittion and receiving operations. These two fifos can be configured as 48 halfwords or 24 words depth
depending on the data word length.
Block Diagram :
TX-FIFO
(48x16/24x32)
FIFO Control
Logic
SCLK/SYNC
& Shift-in/out
control
32-bit CPU bus
32-bit TX-Shift reg
16/32
RX-FIFO
(48x16/24x32)
32-bit RX-Shift reg
16/32
SYNC
SCLK
SDI
SDO
16/32
16/32
Fig 5.1.6-1 SSI Block Diagram
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