
=
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162
Versi on 0. 4, March/2000
contents of the {HI, LO} register, the 64-bit result is placed in {HI, LO} register and GR[t], the bit in
AIR[25] which indicates operating in integer or fraction mode determines the high-order halfword
or low-order halfword of GR[r1], GR[r2] will be as the two operands .
The completer
"
r
"
indicates operating in rounding mode, the multiply result can be
truncated the lower 16 bits when the least 16th bit is zero. IF the the least 16th bit is one, add
one the high-order 16 bits and truncate the low-order 16 bits.
Operation:
Integer mode operation (AIR[25] = 0) :
switch (cmplt) {
case r : (r=1, rounding mode){
GR[t]{0:31}
←
zero_ext(GR[r2]{16:31})
+ 16h8000)){32:63};
{HI, LO}
←
({HI, LO} + (zero_ext(GR[r1]{16:31}) *
zero_ext(GR[r2]{16:31})
+16h8000)){0:63};
break;
}
default : (r=0, unrounding mode){
GR[t]{0:31}
←
{HI,
zero_ext(GR[r2]{16:31}){32:63};
{HI,
LO}
zero_ext(GR[r2]{16:31});
break;
}
}
Fraction mode operation (AIR[25] = 1) :
switch(cmplt) {
case r : (r=1, rounding mode){
GR[t]{0:31}
←
({HI, LO} + lshift(zero_ext(GR[r1]{0:15}) * zero_ext(GR[r2]{0:15}),
1) + 16h8000){32:63};
{HI, LO}
←
({HI, LO} + lshift(zero_ext(GR[r1]{0:15}) *
zero_ext(GR[r2]{0:15}),
1) + 16h8000){0:63};
break;
}
default : (r=0, unrounding mode){
GR[t]{0:31}
←
({HI,
zero_ext(GR[r2]{0:15}),
1)){32:63};
{HI, LO}
←
({HI, LO} + lshift(zero_ext(GR[r1]{0:15}) *
zero_ext(GR[r2]{0:15}),
1)){0:63};
break;
}
}
Exception :
None
({HI,
LO}
+
((zero_ext(GR[r1]{16:31})
*
LO}
+
zero_ext(GR[r1]{16:31})
*
←
{HI,
LO}
+
zero_ext(GR[r1]{16:31})
*
LO}
+
lshift(zero_ext(GR[r1]{0:15})
*