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參數資料
| 型號： | W90221F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器) |
| 中文描述： | PA - RISC的嵌入式微控制器（惠普的PA - RISC結構的32位嵌入式微控制器） |
| 文件頁數： | 9/174頁 |
| 文件大小： | 2102K |
| 代理商： | W90221F |
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The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
9
Versi on 0. 4, March/2000
COMBE[1]/
XWR#
I/O
65
During
PCI
cycles : Bit-1 of command/byte bus
During
AIO
cycles : Asserted low, if INTD# is also low,
indicating a AIO write command cycle is ongoing
During
PCI
cycles : Bit-0 of command/byte bus
During
AIO
cycles : Asserted low, if INTD# is also low,
indicating a AIO read command cycle is ongoing
PCI Interrupt input, level sensitive, low active signal. Once
the INTx# signal is asserted, it remains asserted until the
device driver clear the pending request. When the request is
cleared, the device de-asserts its INTx# signal.
PCI Request input, indicates to the PCI arbiter that this agent
desires use of the bus.
PCI Grant output, indicates to the agent that access to the
bus has been granted.
PCI Reset output, is used to bring PCI-specific registers,
sequencers, and signals to a consistent state. Low active.
PCI Clock output, provides timing for all transactions on PCI
and is an input to every PCI device.
PCI System Error is for reporting address parity errors, data
parity errors on the Special Cycle command, or any other
system error where the result will be catastrophic. The
assertion of SERR# is synchronous to the clock and meets
the setup and hold times of all bused signals.
PCI Parity Error is only for the reporting of data parity errors
during all PCI transactions except a Special Cycle. The
PERR# pin is sustained tri-state and must be driven active
by the agent receiving data two clocks following the data
when a data parity error is detected. The minimum duration
of PERR# is one clock for each data phase that a data parity
error is detected. An agent cannot report a PERR# until it
has claimed the access by asserting DEVSEL# (for a target)
and completed a data phase or is the master of the current
transaction.
PCI Stop indicates the current target is requesting the master
to stop the current transaction.
PCI Target Ready indicates the selected device
complete the current data phase of the transaction. A data
phase is completed on any clock both TRDY# and IRDY# are
sampled asserted. During a read, TRDY# indicates that valid
data is present on PDA[31:0]. During a write, it indicates the
target is prepared to accept data. Wait cycles are inserted
until both IRDY# and TRDY# are asserted together.
PCI Device Select, when actively driven, indicates the
driving device has decoded its address as the target of the
current access. As an input, DEVSEL# indicates whether any
device on the bus has been selected.
COMBE[0]/
XRD#
I/O
47
INTA#, INTB#,
INTC#
I
36, 35, 33
PREQ0#,
PREQ1#
GNT0#
GNT1#
PCIRST#
I
102, 101
O
104, 103
O
23
PCICLK
O
21
SERR#
I
67
PERR#
I/O
68
STOP#
I/O
69
TRDY#
I/O
71
ability to
DEVSEL#
I/O
70
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