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110
Versi on 0. 4, March/2000
Bit 3
This bit has no effects during "peripheral emulation mode", "standard mode",
"fast standard mode" and "PS2 mode".
nACK interrupt enable
0 = Data bus is drived by PPI for forward transferring
1 = Data bus is drived by peripheral device for reverse transferring
Bit 4
Bit 5
Bit 6
Bit 7
This register directly controls several output signals as well as enabling some functions. The power-
on default "0x0" makes {nSelectIn, nInit, nAutoFd, nStrobe} in {high, low, high, high} state, and
8-bit data bus in output enable mode which are suit for "standard mode" transferring.
When this bit is set. A low-to-high transition will generate a interrupt request to CPU core.
Complement version of Parallel Port Interface "nSelectIn" signal
Version of Parallel Port Interface "nInit" signal
Complement version of Parallel Port Interface "nAutoFd" signal
Complement version of Parallel Port Interface "nStrobe" signal
FIFO Status Register (FSR)
Port address : 0xf000037b
Read only
Power-on Default : ---
0
1
2
3
4
5
6
7
Dfifo valid bytes
DA
SA
OV
Bits 0-4 Valid bytes in device data FIFO (Dfifo)
During forward transferring, these bits indicate that how many bytes in 16-byte Dfifo still
not be transfered yet. While during reverse transferring, these bits shows the number of
data bytes which received from parallel port interface and not be read by CPU core.
Bit 5
Dfifo data available
0 = Dfifo contains data bytes less than one "PWord"
1 = Dfifo contains at least one "PWord" of valid data.
Bit 6
Dfifo space available
0 = Dfifo contains empty locations less than one "PWord"
1 = Dfifo contains at least one "PWord" of empty locations.