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157
Versi on 0. 4, March/2000
6 5 5 3 1
1 5 1 5
Purpose:
To multiply corresponding 32-bit sign words of two general registers.
Description:
The corresponding 32-bit sign words of GR[r1] and GR[r2] are arithmetically
multiplied. The multiply results are placed in 64-bit {HI, LO} accumulate register and word result is
placed in GR t. The bit in AIR[25] indicates operating in integer or fraction mode.
The completer,
cmplt
, specified by
"
r
"
indicates operating in rounding mode, the
multiply result can be truncated the lower 32 bits when the least 32th bit is zero. IF the the least
32th bit is one, add one the high-order 32 bits and truncate the low-order 32 bits.
Operation:
Integer mode operation (AIR[25] = 0) :
switch (cmplt) {
case r : (r=1, rounding mode){
GR[t]{0:31}
←
((zero_ext(GR[r1]),
64))+32h80000000){0:31};
{HI, LO}
←
((zero_ext(GR[r1]), 64) * (zero_ext(GR[r2]),
64)+32h80000000;
break;
}
default : (r=0, unrounding mode){
GR[t]{0:31}
←
((zero_ext(GR[r1]), 64) * (zero_ext(GR[r2]), 64)){32:63};
{HI, LO}
←
((zero_ext(GR[r1]), 64) * (zero_ext(GR[r2]), 64));
break;
}
}
Fraction mode operation (AIR[25] = 1) :
switch (cmplt) {
case r : (r=1, rounding mode){
GR[t]{0:31}
←
(lshift((zero_ext(GR[r1]), 64) * (zero_ext(GR[r2]), 64), 1)
+32h80000000){0:31};
{HI, LO}
←
(lshift((zero_ext(GR[r1]), 64) * (zero_ext(GR[r2]), 64),
1)
+32h80000000;
break;
}
default : (r=0, unrounding mode){
GR[t]{0:31}
←
lshift((zero_ext(GR[r1]), 64) * (zero_ext(GR[r2]), 64),
1){0:31};
{HI, LO}
←
lshift((zero_ext(GR[r1]), 64) * (zero_ext(GR[r2]), 64),
1);
break;
}
}
Exception :
None
64)
*
(zero_ext(GR[r2]),