
=
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
170
Versi on 0. 4, March/2000
0:5 6:10 11:1 16:18 19 20
21:25 26 27:31
05
r2
r1
~
r
1
04
6 5 5 3 1
1 5 1 5
Purpose:
To multiply two unsign 32-bit word of GR[r1] and GR[r2], then add accumulate
register {HI, LO} with the multiplied result.
Description:
The corresponding 32-bit word of GR[r1] and GR[r2] are interpretted as unsigned
32-bit operands, and are arithmetically multiplied and add the product with the present contents
of the {HI, LO} register, the 64-bit result is placed in {HI, LO} register. The bit in AIR[25] indicates
operating in integer or fraction mode.
The completer
"
r
"
indicates operating in rounding mode, the multiply result can be truncated
the lower 32 bits when the least 32th bit is zero. IF the the least 32th bit is one, add one the high-
order 32 bits and truncate the low-order 32 bits.
Operation:
Integer mode operation (AIR[25] = 0) :
switch (cmplt) {
case r : (r=1, rounding mode){
GR[t]{0:31}
←
({HI, LO} - (zero_ext(GR[r1]{0:31}) * zero_ext(GR[r2]{0:31})
+ 32h80000000)){0:31};
{HI,
LO}
zero_ext(GR[r2]{0:31})
+32h80000000)){0:63};
break;
}
default : (r=0, unrounding mode){
GR[t]{0:31}
←
zero_ext(GR[r2]{0:31}){32:63};
{HI,
LO}
zero_ext(GR[r2]{0:31});
break;
}
}
Fraction mode operation :
switch(cmplt) {
case r : (r=1, rounding mode){
GR[t]{0:31}
←
({HI,
zero_ext(GR[r2]{0:31}),
1) + 32h80000000){0:31};
{HI, LO}
←
({HI, LO} - lshift(zero_ext(GR[r1]{0:31}) *
zero_ext(GR[r2]{0:31}),
1) + 32h80000000){0:63};
break;
}
default : (r=0, unrounding mode){
~
t
←
({HI,
LO}
-
(zero_ext(GR[r1]{0:31})
*
{HI,
LO}
-
zero_ext(GR[r1]{0:31})
*
←
{HI,
LO}
-
zero_ext(GR[r1]{0:31})
*
LO}
-
lshift(zero_ext(GR[r1]{0:31})
*